1. Field of the Invention
The present invention relates to an abnormal current preventive circuit of a DC-DC converter for determining the presence/absence of an abnormal current such as a countercurrent from an energy-accumulated inductor, an overcurrent of an inductor, etc., and preventing the abnormal current when it is detected.
2. Description of the Related Art
FIG. 1 shows a configuration of a synchronous rectification buck type DC-DC converter which determines the presence/absence of a countercurrent as an abnormal current, and includes a conventional countercurrent preventive circuit for preventing the countercurrent when it is detected. In FIG. 1, the configuration includes: an input power source terminal (VIN terminal) 101; a feedback voltage input terminal (FB-IN terminal) 102 to which a feedback voltage detected after dividing an output voltage (OUTPUT) supplied to a load not shown in FIG. 1 by a resistor R3 (117) and a resistor R2 (118) is input; an output terminal (OUT terminal) 103 of a circuit for controlling energy accumulation/release (hereinafter energy accumulation is referred to as ‘charge’, and energy release as ‘discharge’); a ground terminal (GND terminal) 104; an oscillator (OSC) 105 for outputting a clock signal; a ramp generator 106 for generating a ramp signal Vramp by a trigger of the output of the oscillator (OSC) 105; an error amp 108 for comparing a feedback voltage with a reference voltage VREF1 (107) and outputting an error signal Verror; a PWM (pulse-width modulation) comp 109 for comparing an output Verror of the error amp 108 with the output Vramp of the ramp generator 106, converting a control signal into a pulse width and outputting a conversion result; a driver 110 for driving a high-side switching device (Q31) 113 for control of a charging period of an inductor L1 (115), a low-side switching device (Q32) 114 for controlling the charging period of the inductor L1 (115), and a switching device (Q33) 119; a voltage comparator 111 for comparing a voltage of a detection resistor 112 with GRD potential and determining the presence/absence of a countercurrent; a resistor 112 for detecting a countercurrent of an inductance current when the low-side switching devices 114 and 119 are in the ON states; a smoothing capacitor (Cout) 116 for obtaining an output voltage; and an AND circuit 120 for placing the low-side switching devices 114 and 119 in the OFF states when a countercurrent flows from the inductor L1 (115). The high-side switching device (Q31) 113 is configured by a Pch MOSFET, and the low-side switching device (Q32) 114 and the switching device (Q33) 119 are configured by an Nch MOSFET. A Pch MOSFET is short for a P-channel metal oxide semiconductor field effect transistor, and an Nch MOSFET is short for an N-channel metal oxide semiconductor field effect transistor.
In FIG. 1, the output voltage OUTPUT of the DC-DC converter is divided by the resistor R3 (117) and the resistor R2 (118), and applied to the feedback voltage input terminal 102. The feedback voltage and the reference voltage VREF1 (107) are compared by the error amp 108, and transmitted to the PWM comp 109 as an error signal Verror. The PWM comp 109 compares the error signal Verror with the output Vramp of the ramp generator 106, and transmits an output signal that places the high-side switching devices 113 in the ON states to the driver 110 when Verror>Vramp and places the low-side switching devices 114 and 119 in the ON states to the driver 110 when Verror<Vramp. The driver 110 drives a switching device according to the output signal of the PWM comp 109, but basically turns ON/OFF (inversely) the high-side switching devices 113 and the low-side switching devices 114 and 119 complementarily, and does not turn them ON simultaneously (for setting a dead time), thereby realizing a non-overlap function.
When the high-side switching device 113 is placed in the ON states, the inductor L1 (115) is charged by the power source 101. When the low-side switching devices 114 and 119 are placed in the ON states, the inductor L1 (115) is discharged through the load and the low-side switching devices 114 and 119. In the charge/discharge cycle, when the output voltage OUTPUT is low, the output voltage Verror of the error amp 108 becomes high. As a result, the ON duty ratio of the high-side switching device 113 becomes high, and the ON period of the low-side switching devices 114 and 119 becomes short, thereby enhancing the output voltage OUTPUT. On the other hand, when the output voltage OUTPUT is high, an inverse result occurs, the ON duty ratio of the high-side switching device 113 becomes low, and the ON period of the low-side switching devices 114 and 119 becomes long, thereby reducing the output voltage OUTPUT. By repeating the cycle, the control circuit functions to constantly keep the voltage of the feedback voltage input terminal 102 equal to the reference voltage 107, thereby controlling the output voltage OUTPUT to be expressed by the following equation (1).Vout=VREF1*(1+R3/R2)  (1)
(where VREF1 indicates the voltage of the reference voltage 107)
In FIG. 1, when the ON period of the low-side switching devices 114 and 119 is long, and the energy of the inductor 115 becomes exhausted, the inductor L1 (115) is charged from the smoothing capacitor 116 through the low-side switching devices 114 and 119. Thus, the inductance current of the inductor 115 inversely flows as a countercurrent. Although the voltage of the detection resistor 112 is normally a negative voltage, it is a positive voltage when a countercurrent occurs. When the countercurrent flows, the output voltage of the voltage across the smoothing capacitor 116 suddenly falls because the source of the countercurrent is the electric charge accumulated in the smoothing capacitor 116. Passing the electric charge accumulated in the smoothing capacitor 116 inversely in the inductor 115 refers to discarding the energy accumulated in the smoothing capacitor 116, that is, a loss of electric power of the DC-DC converter. Therefore, the low-side switching devices 114 and 119 that receive the countercurrent are to be turned OFF to prevent the countercurrent. It is performed by the voltage comparator 111 and the AND circuit 120. The voltage comparator 111 compares the voltage of the detection resistor 112 with the GND level, transmits the high output to the AND circuit 120 while the voltage of the detection resistor 112 is negative so that the output signal of the driver 110 can be transmitted to the low-side switching devices 114 and 119. When the voltage of the detection resistor 112 becomes a positive voltage, the output voltage of the voltage comparator 111 becomes low, thereby forcibly turning OFF the low-side switching devices 114 and 119.
It is expected that an ideal countercurrent detecting operation by the voltage comparator 111 can be performed when there is no delay time of the voltage comparator. However, the delay time of the voltage comparator cannot be avoided, and the ideal operation cannot be expected. According to the simulation of the inventor, the delay time of the voltage comparator with the normal configuration is 200˜300 ns. The delay time of 200˜300 ns refers to the delay time of the timing with which the low-side switching devices 114 and 119 is turned OFF, and the countercurrent flows through the inductor 115 during the time. Since the recent tendency of DC-DC converters is the clock frequency of 1 MHz or more, that is, the switching period of 1000 ns or less, the influence has become serious. That is, the fluctuation of the output voltage of the DC-DC converters has become large, thereby degrading operation efficiency.
In the description above, the countercurrent from an energy-accumulated inductor is described. There is a similar problem with the overcurrent of an inductor where, for example, a voltage comparator shown in FIG. 1 is applied as is to a boost type DC-DC converter.
FIG. 2 shows the configuration of a boost type DC-DC converter for including a conventional overcurrent preventive circuit for determining the presence/absence of an overcurrent as an abnormal current to prevent the overcurrent when it is detected. In FIG. 2, the configuration includes: an input power source terminal (VIN terminal) 201; a feedback voltage input terminal (FB-IN terminal) 202 to which a feedback voltage detected after dividing an output voltage (OUTPUT) supplied to a load not shown in FIG. 2 by a resistor R3 (217) and a resistor R2 (218) is input; an output terminal (OUT terminal) 203 of a circuit for controlling energy accumulation/release (hereinafter energy accumulation is referred to as ‘charge’, and energy release as ‘discharge’); a ground terminal (GND terminal) 204; an oscillator (OSC) 205 for outputting a clock signal; a ramp generator 206 for generating a ramp signal Vramp by a trigger of the output of the oscillator (OSC) 205; an error amp 208 for comparing a feedback voltage with a reference voltage VREF1 (207) and outputting an error signal Verror; a PWM (pulse-width modulation) comp 209 for comparing an output Verror of the error amp 208 with the output Vramp of the ramp generator 206, converting a control signal into a pulse width and outputting a conversion result; a latch device 210 set according to the overcurrent detection signal of a voltage comparator 211 for turning OFF a switching device (Q32) 214 and a switching device (Q33) 219 by transmitting a signal to an AND circuit 220; the voltage comparator 211 for comparing the voltage of a detection resistor (R1) 212 with a reference voltage VREF2 (221) to determine the presence/absence of an overcurrent; a resistor 212 for detecting an inductance current while the switching devices 214 and 219 are placed in the ON states; a diode (D1) 213 for preventing the boosted output voltage (OUTPUT) from being a countercurrent to the power source 201; a smoothing capacitor (Cout) 216 for obtaining an output voltage (OUTPUT); and the AND circuit 220 for driving the switching devices 214 and 219 for controlling the charging period of the inductor L1 (215).
In FIG. 2, when the switching devices 214 and 219 are placed in the ON states, a charge current passes from the power source 201 to the inductor 215, and the energy is accumulated. When the switching devices 214 and 219 are placed in the OFF states, the energy accumulated in the inductor 215 is supplied to the smoothing capacitor 216 on the output side and a load through the diode 213. The output voltage (OUTPUT) of the DC-DC converter is divided by the resistor R3 (217) and the resistor R2 (218) and applied to the feedback voltage terminal 202, and the feedback voltage and the reference voltage VREF1 (207) is compared by the error amp 208, and transmitted as an error signal Verror to the PWM comp 209. The PWM comp 209 compares the error signal Verror with Vramp as the output of the ramp generator 206. If Verror>Vramp, the switching devices 214 and 219 are placed in the ON states. If Verror<Vramp, the switching devices 214 and 219, an output signal for placing the switching devices 214 and 219 in the OFF states is transmitted to the AND circuit 220.
When the output voltage (OUTPUT) is low, the output voltage Verror becomes high, the ON duty ratio of the switching devices 214 and 219 becomes high, and the OFF period of the switching devices 214 and 219 becomes short, thereby enhancing the output voltage (in the normal continuous mode of the boost type DC-DC converter, the output voltage (OUTPUT)=VIN*(Ton+Toff) where Ton and Toff respectively indicate the ON period and the OFF period of the switching devices 214 and 219). On the other hand, when the output voltage (OUTPUT) is high, the inverse results are obtained, that is, the ON duty ratio becomes low, and the OFF period of the switching devices 214 and 219 becomes long, thereby lowering the output voltage. By repeating the cycle, the control circuit functions to constantly keep the voltage of the feedback voltage input terminal 202 equal to the reference voltage VREF1 (207), and the output voltage is controlled as a value expressed by the equation (1) above.
In FIG. 2, if the ON period of the switching devices 214 and 219 is long, the current flowing through the inductor 215 increases with the lapse of time, and the drain current of the switching devices 214 and 219 exceeds the maximum rating, then there is a strong possibility that the switching device 214 is destroyed. Normally, to restrict the drain current before it reaches the maximum rating, the switching device 219 that is similar to and has 1/N gate width of the switching device 214 is connected in parallel, and the detection resistor (R1) 212 is interposed between the source and the GND (ground) to monitor the drain current of the switching device 214 by the voltage comparator 211. The switching device 219 is used because it is necessary to reduce the resistance value of the detection resistor R1 (212) down to 1Ω or less to face the large drain current when the detection resistor 212 is connected between the source of the switching device 214 and the GND. The required resistance cannot be manufactured by an IC.
The voltage of the detection resistor 212 is proportional to the inductance current of the switching devices 214 and 219 in the ON period. If the voltage comparator 211 compares the voltage with the reference voltage VREF2 (221), and the voltage of the resistor exceeds the reference voltage VREF2 (221), then the presence of an overcurrent is determined, the output (CP OUT) of the voltage comparator 211 is inverted into a low state, and the output D0 of the latch device 210 is placed in the low state. The output D0 of the latch device 210 is placed in the high state in advance according to a reset signal. Then, since the output D0 is connected to another input terminal of the AND circuit 20, the switching devices 214 and 219 are turned off to prevent the drain current (overcurrent). The operation is normally performed in every cycle of the clock signal, and the latch device 210 is reset at every reset signal.
Thus, although the overcurrent is avoided as described above, the overcurrent detecting operation of the voltage comparator 211 shown in FIG. 2 can be ideally performed when there is no delay time of the voltage comparator as described above with reference to the voltage comparator 111 in detecting a countercurrent with reference to FIG. 1. However, the delay time of the voltage comparator cannot be actually avoided, and the ideal operation cannot be expected. Therefore, the switching device 214 can be destroyed with a high probability. Accordingly, it is necessary to take countermeasures to increase a margin by reducing the set value of the overcurrent against the delay time. One of the countermeasures to increase a margin is to make a larger switching device 214, and another is to increase the bias current of the voltage comparator to shorten the delay time.
Thus, the presence/absence of an abnormal current such as a countercurrent from an inductor, an overcurrent of an inductor, etc. is determined using a voltage comparator. However, in the patent document 1 described below proposes a current direction detection circuit for preventing a countercurrent as an abnormal current, and operates the current direction detection circuit not by a voltage, but by a current mode (the signal for the operation is not a voltage signal but a current signal), thereby succeeding in operating it as a smaller circuit in a shorter delay time.
The delay time with the above-mentioned conventional voltage comparator fluctuates depending on the device characteristic normally caused by the manufacturing process of an IC, it is necessary to set a large margin, thereby causing the problem that the sizes of the switching devices shown in FIGS. 1 and 2 unnecessarily increase and that the cost also increases. In addition, when the bias current is increased to shorten the delay time in the conventional voltage comparator, the power consumption increases and the operation efficiency is degraded.
With the current direction detection circuit having the countercurrent preventive function disclosed by the patent document 1, there is the problem that the characteristic cannot be stable because the influence of the device fluctuation on the characteristic is large.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2005-237099